preliminary maximum ratings (t a =25c) symbol units drain-source voltage v ds 50 v drain-gate voltage v dg 50 v gate-source voltage v gs 40 v continuous drain current i d 300 ma maximum pulsed drain current i dm 1.2 a power dissipation p d 350 mw (note 1) power dissipation p d 300 mw (note 2) power dissipation p d 150 mw (note 3) operating and storage junction temperature t j ,t stg -65 to +150 c thermal resistance ja 357 c/w electrical characteristics per transistor (t a =25c unless otherwise noted) symbol test conditions min typ max units i gssf, i gssr v gs =5v 50 na i gssf, i gssr v gs =10v 500 na i gssf, i gssr v gs =12v 1.0 a i dss v ds =50v, v gs =0v 50 na bv dss v gs =0v, i d =10a 50 v v gs(th) v ds =v gs , i d =250a 0.5 1.2 v r ds(on) v gs =1.8v, i d =50ma 1.6 2.3 r ds(on) v gs =2.5v, i d =50ma 1.3 1.9 r ds(on) v gs =5.0v, i d =50ma 1.1 1.5 g fs v ds =10v, i d =200ma 200 mmhos c rss v ds =25v, v gs =0, f=1.0mhz tbd pf c iss v ds =25v, v gs =0, f=1.0mhz tbd pf c oss v ds =25v, v gs =0, f=1.0mhz tbd pf v sd v gs =0v, i s =115ma 1.4 v CMLDM7003 CMLDM7003j surface mount picomini tm dual n-channel enhancement-mode silicon mosfet sot-563 case central semiconductor corp. tm r0 (26-june 2006) description: the central semiconductor CMLDM7003 and CMLDM7003j are enhancement-mode n-channel field effect transistors, manufactured by the n-channel dmos process, designed for high speed pulsed amplifier and driver applications. the CMLDM7003 utilizes the usa pinout configuration, while the CMLDM7003j utilizes the japanese pinout configuration. these special dual transistor devices offer low drain-source on state resistance (r ds(on) ). marking code: CMLDM7003: c30 CMLDM7003j: c3j notes: (1) ceramic or aluminum core pc board with copper mounting pad area of 4.0 mm 2 (2) fr-4 epoxy pc board with copper mounting pad area of 4.0 mm 2 (3) fr-4 epoxy pc board with copper mounting pad area of 1.4 mm 2
preliminary central semiconductor corp. tm sot-563 case - mechanical outline CMLDM7003 CMLDM7003j surface mount picomini tm dual n-channel enhancement-mode silicon mosfet r0 (26-june 2006) lead code: 1) gate q1 2) source q1 3) drain q2 4) gate q2 5) source q2 6) drain q1 marking code: c30 lead code: 1) source q1 2) gate q1 3) drain q2 4) source q2 5) gate q2 6) drain q1 marking code: c3j CMLDM7003 (usa pinout) CMLDM7003j (japanese pinout)
|
